As is well known, bipolar transistors, in their most elemental form, comprise a sandwich made up of three layers of semiconducting material, the middle layer being of an opposite conductivity type to the outer layers. Much work has been done on optimizing both the dimensions of these layers as well as determining the best way to distribute dopants within them. For the particular case of transistors that have been optimized for operation at high voltages, the form of the device is somewhat more complicated than for a 'simple' device intended to handle low voltage signals.
An example of such a device (of the prior art), for an NPN version, is illustrated in FIG. 1. Silicon body 2 may be an N type wafer or (as shown here) an N well that has been formed within silicon wafer 1. P Me base layer 3 extends downward from the surface into N type silicon 2. Within 3 are both N+ emitter 4 and a P+ base contact 5, the two being separated from each other by field oxide 9. A key feature of this design is that, although 2 serves as the collector it has relatively high resistivity and therefore introduces a high series resistance to the device. This problem is overcome by the introduction of a buried subcollector 6 of N+ material that is accessed at its ends through plugs, or sinkers, 8 which are themselves contacted through the N+ regions 7. The various contact regions 4, 5, and 7 are all separated from one another by field oxide 9.
This design suffers from several disadvantages including low BV.sub.ceo and low early voltage. A particular disadvantage is that the formation of layer 2 requires the deposition of at least 10 microns of epitaxial silicon as part of the manufacturing process. Deposition of such a thick layer can take as long as 10 minutes, thereby adding significantly to the total manufacturing cost.
An alternative design that does not require the presence of a buried collector layer is the use of silicon on insulator (SOI) technology, an example of which is shown in FIG. 2. In this design, the main components of the device are the same as in the previous example with layer 22 serving as the collector, contacted through N+ region 7. Surrounding the entire device is insulating layer 21 which is itself embedded within silicon wafer 1. This approach, while effective, is significantly more expensive than more conventional approaches, including even the device of FIG. 1.
In FIG. 3 we show equipotential lines inside a conventional device having a V.sub.EB of about 0.7 volts and a V.sub.BC of about 8 volts. As can be seen, in the general area pointed to by arrow 31, the equipotential lines are more crowded together, indicating a high voltage gradient and, therefore, the area in which voltage breakdown will occur first.
FIG. 4 shows curve 41 which plots collector current as a function of collector voltage, showing that breakdown occurs at about 10 volts for the conventional structure.
In the course of searching the prior art, no references that teach the structure and process of the present invention were found. A number of references of interest were, however, encountered. Two examples of SOI technology that we found were Jerome et al. (U.S. Pat No. 5,344,785) who disclose a high-speed, high voltage fully isolated bipolar transistor on an insulating substrate and U.S. Pat. No. 5,536,961 in which Nakagawa el. teach the use of dielectric isolation as a means to increase breakdown voltage, their device including high and low resistance lateral sections.
Litwin (U.S. Pat. No. 5,659,190) takes a somewhat different approach and uses a combination of a bipolar and a field effect transistor to improve breakdown voltage, showing how the two devices can be combined to fit in a small space.
Depetro et al. (U.S. Pat. No. 5,852,314) shows MOS devices with a variable length of buried layers that exploit RESURF conditions. It is not applicable to bipolar devices. Ratnakumar (U.S. Pat. No. 5,011,784) also shows a bipolar transistor with a buried region.